Add sampler slots usage and inputs/outputs count to GPU shader program bindings meta

This commit is contained in:
Wojtek Figat
2026-02-26 12:02:52 +01:00
parent ac4526744a
commit 20c9ed27fb
7 changed files with 35 additions and 14 deletions

View File

@@ -112,15 +112,13 @@ bool GPUPipelineState::Init(const Description& desc)
#endif
// Cache shader stages usage flags for pipeline state
_meta.InstructionsCount = 0;
_meta.UsedCBsMask = 0;
_meta.UsedSRsMask = 0;
_meta.UsedUAsMask = 0;
Platform::MemoryClear(&_meta, sizeof(_meta));
#define CHECK_STAGE(stage) \
if (desc.stage) { \
_meta.UsedCBsMask |= desc.stage->GetBindings().UsedCBsMask; \
_meta.UsedSRsMask |= desc.stage->GetBindings().UsedSRsMask; \
_meta.UsedUAsMask |= desc.stage->GetBindings().UsedUAsMask; \
_meta.UsedSamplersMask |= desc.stage->GetBindings().UsedSamplersMask; \
}
CHECK_STAGE(VS);
CHECK_STAGE(HS);

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@@ -215,6 +215,14 @@ public:
return _meta.UsedUAsMask;
}
/// <summary>
/// Gets texture samplers mask (each set bit marks usage of the sampler slot at the bit index slot). Combined from all the used shader stages.
/// </summary>
FORCE_INLINE uint32 GetUsedSamplersMask() const
{
return _meta.UsedSamplersMask;
}
public:
/// <summary>
/// Returns true if pipeline state is valid and ready to use

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@@ -12,7 +12,7 @@ class GPUShaderProgram;
/// <summary>
/// The runtime version of the shaders cache supported by the all graphics back-ends. The same for all the shader cache formats (easier to sync and validate).
/// </summary>
#define GPU_SHADER_CACHE_VERSION 12
#define GPU_SHADER_CACHE_VERSION 13
/// <summary>
/// The GPU resource with shader programs that can run on the GPU and are able to perform rendering calculation using textures, vertices and other resources.

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@@ -21,6 +21,9 @@ struct FLAXENGINE_API ShaderBindings
uint32 UsedCBsMask;
uint32 UsedSRsMask;
uint32 UsedUAsMask;
uint32 UsedSamplersMask;
uint16 InputsCount;
uint16 OutputsCount;
FORCE_INLINE bool IsUsingCB(uint32 slotIndex) const
{
@@ -36,6 +39,11 @@ struct FLAXENGINE_API ShaderBindings
{
return (UsedUAsMask & (1u << slotIndex)) != 0u;
}
FORCE_INLINE bool IsUsingSampler(uint32 slotIndex) const
{
return (UsedSamplersMask & (1u << slotIndex)) != 0u;
}
};
struct GPUShaderProgramInitializer

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@@ -79,6 +79,9 @@ namespace
{
bool ProcessShader(ShaderCompilationContext* context, Array<ShaderCompiler::ShaderResourceBuffer>& constantBuffers, ID3D11ShaderReflection* reflector, D3D11_SHADER_DESC& desc, ShaderBindings& bindings)
{
bindings.InputsCount = desc.InputParameters;
bindings.OutputsCount = desc.OutputParameters;
// Extract constant buffers usage information
for (uint32 a = 0; a < desc.ConstantBuffers; a++)
{
@@ -131,13 +134,12 @@ namespace
{
// Sampler
case D3D_SIT_SAMPLER:
bindings.UsedSamplersMask |= 1 << resDesc.BindPoint;
break;
// Constant Buffer
case D3D_SIT_CBUFFER:
case D3D_SIT_TBUFFER:
break;
// Shader Resource
case D3D_SIT_TEXTURE:
case D3D_SIT_STRUCTURED:
@@ -145,7 +147,6 @@ namespace
for (UINT shift = 0; shift < resDesc.BindCount; shift++)
bindings.UsedSRsMask |= 1 << (resDesc.BindPoint + shift);
break;
// Unordered Access
case D3D_SIT_UAV_RWTYPED:
case D3D_SIT_UAV_RWSTRUCTURED:
@@ -316,7 +317,7 @@ bool ShaderCompilerD3D::CompileShader(ShaderFunctionMeta& meta, WritePermutation
additionalDataVS.Inputs.Add({ ParseVertexElementType(inputDesc.SemanticName, inputDesc.SemanticIndex), 0, 0, 0, format });
}
}
ShaderBindings bindings = { desc.InstructionCount, 0, 0, 0 };
ShaderBindings bindings = { desc.InstructionCount };
if (ProcessShader(_context, _constantBuffers, reflector.Get(), desc, bindings))
return true;

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@@ -372,7 +372,9 @@ bool ShaderCompilerDX::CompileShader(ShaderFunctionMeta& meta, WritePermutationD
}
DxShaderHeader header;
Platform::MemoryClear(&header, sizeof(header));
ShaderBindings bindings = { desc.InstructionCount, 0, 0, 0 };
ShaderBindings bindings = { desc.InstructionCount };
bindings.InputsCount = desc.InputParameters;
bindings.OutputsCount = desc.OutputParameters;
for (uint32 a = 0; a < desc.ConstantBuffers; a++)
{
auto cb = shaderReflection->GetConstantBufferByIndex(a);
@@ -422,13 +424,12 @@ bool ShaderCompilerDX::CompileShader(ShaderFunctionMeta& meta, WritePermutationD
{
// Sampler
case D3D_SIT_SAMPLER:
bindings.UsedSamplersMask |= 1 << resDesc.BindPoint;
break;
// Constant Buffer
case D3D_SIT_CBUFFER:
case D3D_SIT_TBUFFER:
break;
// Shader Resource
case D3D_SIT_TEXTURE:
for (UINT shift = 0; shift < resDesc.BindCount; shift++)
@@ -445,7 +446,6 @@ bool ShaderCompilerDX::CompileShader(ShaderFunctionMeta& meta, WritePermutationD
header.SrDimensions[resDesc.BindPoint + shift] = D3D_SRV_DIMENSION_BUFFER;
}
break;
// Unordered Access
case D3D_SIT_UAV_RWTYPED:
case D3D_SIT_UAV_RWSTRUCTURED:

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@@ -728,7 +728,9 @@ bool ShaderCompilerVulkan::CompileShader(ShaderFunctionMeta& meta, WritePermutat
void* additionalData = nullptr;
SpirvShaderHeader header;
Platform::MemoryClear(&header, sizeof(header));
ShaderBindings bindings = { 0, 0, 0, 0 };
ShaderBindings bindings = {};
bindings.InputsCount = program.getNumPipeInputs();
bindings.OutputsCount = program.getNumPipeOutputs();
if (type == ShaderStage::Vertex)
{
additionalData = &additionalDataVS;
@@ -822,6 +824,10 @@ bool ShaderCompilerVulkan::CompileShader(ShaderFunctionMeta& meta, WritePermutat
switch (descriptor.BindingType)
{
case SpirvShaderResourceBindingType::SAMPLER:
ASSERT_LOW_LAYER(descriptor.Slot >= 0 && descriptor.Slot < GPU_MAX_SAMPLER_BINDED);
bindings.UsedSamplersMask |= 1 << descriptor.Slot;
break;
case SpirvShaderResourceBindingType::CB:
ASSERT_LOW_LAYER(descriptor.Slot >= 0 && descriptor.Slot < GPU_MAX_CB_BINDED);
bindings.UsedCBsMask |= 1 << descriptor.Slot;